DC Coupled Amplifiers for Audio


We will here look at DC coupled amplifiers. We will start with the differential stage, and continue with the voltage feedback operational amplifier. Finally we will look at the current feedback amplifier.

The differential amplifier is one of the most important amplifying stages within linear circuit theory. It has several properties which makes it well suited as the input stage in amplifiers, e.g. it is always used in operational amplifiers with voltage feedback.

In addition one may mention the stages ability to suppress even large noise signals superimposed on a relatively weak input signal.

Beyond that the stage has a relatively small DC drift making it well suited as DC amplifier. The extra high impedance input terminal is among other ideal for applying a feedback signal.

When adding that the stage is suitable as  a balanced mixer and modulator, one may see that the stage is a widely applicable building block.

The current feedback operational amplifier is a relatively new invention. It is characterized by very large speed  (high 'Slew Rate' value) and very large bandwidth compared to the conventional voltage feedback operational amplifier. However, the accuracy is somewhat inferior, mainly due to a low impedance inverting input.


We here will concentrate on the application as a small signal amplifier for the differential stage. Generally spoken the function of the differential amplifier is to amplify the difference between to signals. The principle of a differential amplifier stage is shown in figure 2.1.


Figure 2.1. Differential amplifier with input signal.

We want to amplify the signal voltage uD. Since this not has any direct ground connection, it is called a differential input voltage.

Unfortunately the signal voltage is often superimposed by an unwanted common mode noise voltage uCM. The noise voltage uCM in reality may be a result of earth loops, inductive or capacitive noise accumulation and so on. The phenomena is illustrated in figure 2.2, in this example the noise voltage is greater than the signal voltage.

The ideal differential amplifier will have high gain for the signal voltage uD, but will cause an infinite attenuation of the noise voltage uCM. Figure 2.2a shows the wanted signal uD to be amplified. The signal may be measured between the amplifiers input terminals 1 og 2. The signal is shown here with a frequency of 1 kHz.


Figure 2.2a. Wanted signal voltage uD.

Figure 2.2b shows the unwanted earth loop signal uCM, which is caused by the potential difference between to ground references. The signal may be measured between the amplifiers input terminal 2 and ground. The signal is here shown with a frequency of 50 Hz (e.g. as a result of mains hum), observe the amplitude.


Figure 2.2b. Unwanted noise voltage uCM.

Figure 2.2c shows the resulting signal u1, which may be measured between the amplifiers input terminal 1 and ground, notice that the noise voltage contribution is dominating.


Figure 2.2c. Resulting input voltage u1 at the amplifiers input terminal.

Differential gain is given by (figure 2.1):

AD = uO/uD


Common Mode gain is given by:

ACM = uO/uCM


It is required that ACM is as close to 0 as possible. In reality  ACM will have a value greater than 0, but less than 1. Hence it is defined a figure giving the quality of the practical differential amplifier, known as the Common Mode Rejection Ratio, CMRR. This is normally given in dB and is defined as:

CMRR = 20 lg |AD/ ACM|


The measurement set-up in figure 2.3 is employed to measure AD and ACM. In other words it is desirable that CMRR has a highest possible value.





Figure 2.3. Measurement set-up to measure AD (a) and ACM (b), respectively.

CMRR is one of the most important figures for operational amplifiers for instance. Here it is the first stage, the differential amplifier, that gives this value. Typical values are 90-100 dB for the most common operational amplifiers.


Figure 2.4 shows a typical differential amplifier stage. The stage is supplied from two symmetrical power supplies. In this stage a large voltage drop across R0 is wanted.


Figur 2.4. The differential amplifier stage.

The base resistors RB1 and RB2 keep the bases to nearly ground potential. Often it is wanted to connect the signal source and amplifier directly, to avoid coupling capacitor (and base resistors).

Emitter degeneration by means of RE1 and RE2 is necessary with discrete design, large signal inputs and/or signal inputs running on high frequency (e.g. video signals).

As seen, it is various ways to output the signal. Either one may use the differential voltage, uOD = uC2 - uC1, between the collectors as an output, or one may use the single ended voltage uO = uC1 or uC2 as an output.

In the ideal differential amplifier the transistors would be completely equal, fulfilling the following requirements:

IC1 = IC2, hFE1 = hFE2, UBE1 = UBE2, 1 = 2 (gm1 = gm2).



These requirements it is, however, not possible to meet, but it is possible to get closer by integrating the two transistors on the same chip.

The mode of operation is most easily explained by imaging that uD at a given time has the polarity as indicated in the figure. The base of transistor Q1 thus moves positive, while the base of Q2 moves negative. Thus IC1 will increase and IC2 will decrease with the same numerical value.

The result is two equal, but opposite, collector voltage changes uC1 and uC2. If the output signal is the difference signal uOD, the double output voltage swing is available.

As the collector current changes in Q1 and Q2 have the same numerical value, but of opposite polarity, the current in R0 is constant. There is in other words no signal current, caused by the differential input voltage uD, in this resistor.

Feeding the stage with a common mode signal uCM when uD = 0, the two bases will follow each other. The voltage uCM is transferred directly to R0, and a signal current will run in the resistor. This current will split in two equal emitter currents for the two transistors.

The result is two in phase identical collector voltage changes. Using a differential output, uOD thus is 0, i.e. uCM is suppressed at the output. With single ended output, as mentioned, the two collector signal voltages uC1 and uC2 are present.


Here we will look at the differential amplifiers DC conditions, see figure 2.5. Assuming hFE >> 1, we may neglect the base currents. At the same time we are assuming equal transistors, such that hFE1 = hFE2 and UBE1 = UBE2.


Figure 2.5. DC equivalent for the differential amplifier stage.

The total emitter current is given by:



For equal transistors, I0 is divided equally between Q1 and Q2. This gives:

IC1 = IC2 = I0/2


As the two collector resistors are equal, this gives:



In reality the two transistors will have different hFE, and at he same time there will be different UBE for the two transistors. The result is a certain imbalance between IC1 and IC2.

Applying a common mode signal with large amplitude to the stage in figure 2.5, the voltage changee across R0 will be accordingly large. This implies that IC1 and IC2 may vary that much that Q1 and Q2 in worst case is saturated. Therefore R0 usually is replaced by a constant current generator. This may be carried out as simple as shown in figure 2.6.


Figure 2.6. Differential stage with constant current generator.

Q3 operate as the constant current generator as its base is kept at a fixed potential by means of the "stiff" voltage divider consisting of R1 and R2. The voltage across R3, and accordingly the collector current in Q3, thus is constant and nearly independent of an eventually common mode input voltage change. It is seen that IC3 = I0.

The DC design must provide for a choice of the voltage across R3 to ensure a minimum collector emitter voltage for Q3, even at the greatest possible negative common mode input voltage swing.

The dynamic output impedance of the current generator is very high, as in reality Q3 is working in common base mode. Because of the capacitor C this is given by:

Ro = rce



Here we will look closer at the small signal properties of the differential stage. Firstly we will look at the response for a differential input signal, secondly at a common mode input signal. In figure 2.7 is shown the diagram for the stage we want to analyse.


Figure 2.7. The differential stage with emitter degeneration.

Assuming equal transistors and resistors, this implies that both transconductanse and current gain are equal for the two transistors.

2.3.1. Differential input signal.

Since ig = ib1 = -ib2, the differential input voltage for >>1 is given by:

uD = 2ig(rbe + RE)


The two collector voltages uc1 and uc2 are given by:

uc1 = -igRC



uc2 = igRC


Notice that these two signals have opposite phase. Thus it is seen that the differential stage may be divided in two separate parts, where the point A is at virtual ground. The differential output signal is therefore:

uOD = uc2 - uc1 = 2igRC


The differential gain (given by 2.1) thus becomes:

AD = uOD / uD = RC/(rbe + RE)


If the output is single ended, e.g. as uC2, the gain is given by:

ASD = uC2/uD = RC/2(rbe + RE)


As expected we here have half the gain of AD. The differential input resistance seen from the generator is given by:

RiD = uD/ ig = 2(rbe + RE)


2.3.2. Common Mode input signal.

Seen from the common mode generator the two bases are parallel coupled. The generator current is consequently the sum of the two base currents, ig = ib1 + ib2. When the transistors are equal, the common mode input voltage (for >>1) is given by:

uCM = ib(rbe + RE) + 2ibR0


The two collector voltages uc1 and uc2 are given by:

uc1 = uc2 = -ibRC


Notice that these two signals now are in phase. Accordingly the differential stage now also may be separated in two equal parts, but where the point now is following the signal. The differential output signal therefore is:

uOD = uc2 - uc1 = 0


For the ideal differential amplifier the following therefore is valid (given by 2.1):

ACM = uOD/uCM = 0


A single ended output signal, e.g. uC2, gives the following gain:

ASCM = uC2/uCM = -RC/2(rbe + RE + 2R0)


Compared to the differential gain, it is seen that the common mode gain is much lower than the differential gain. This is just the wanted property of the differential amplifier. At the same time eq. 2.18 shows that if R0 is made very large, ASCM becomes very small. In reality this means that uCM is heavily suppressed. By using a current generator instead of R0 (e.g. as shown in figure 2.6), this is possible to achieve.

As both AD and ACM now are known figures, the stages common mode rejection ratio may be calculated. CMRR for differential output was defined as:

CMRR = 20 lg |AD/ACM|


Given differential output signal, ACM = 0 here. Accordingly CMRR in theory is infinite. Since we have assumed equal transistors, the practical value is lower. CMRR for single ended output in the same way may be defined as:

CMRR = 20 lg |ASD/ASCM|


Inserting for ASD og ASCM gives:

CMRR = 20 lg [(rbe + RE + 2R0)/(rbe + RE)]


To get a high value for CMRR, R0 should be large. This is, as mentioned, achieved by replacing R0 with a current generator. Additionally another advantage is achieved: the quiescent point and CMRR become nearly independent.

In addition is another aspect which earlier not has been considered. Often the properties of an amplifier are a result of the used power supply. An amplifier may be designed to be power supply dependent, or it may be designed to suppress unwanted noise products stemming from the power supply. The power supply rejection ratio (PSRR) indicate how good an amplifier is designed to prevent noise from the power supply to reach the amplifier output.

A current generator replacing R0 is preferred as the amplifier would have a much higher PSRR value than with a single resistor.


Here we will continue with a complete design of a typical operational amplifier. One option is shown in figure 3.1. It should be pointed out that the design also might be used in other applications. E.g. with an increase of the current capacity and the power supply voltages, the design may be used as an audio power amplifier.


Figure 3.1. Typical operational amplifier with voltage feedback.

The design shown in figure 3.1 may be separated in three parts:


The input stage is a differential stage with a single ended output. As earlier mentioned a differential stage will have nearly 0 volt at the input. Accordingly the offset voltage is relatively low. Aside from a much lower offset voltage due to the cancellation of the impact from the base emitter voltages, the differential stage in addition has the advantage that a part of the quiescent current not has to run through an eventually feedback network. In addition the linearity is much better than for an input stage consisting of a single transistor stage.

Notice that the two collector resistors are replaced by a current mirror. Since the signal output is single ended, the use of resistors would cause imbalance between the two transistors in the differential stage. Another result of the use of the current mirror, is that the transconductance is doubled compared to the use of resistors.

If the transconductance for the transistor is gm, the transconductance with emitter degeneration is gm/(1 + gmRE), assuming >>1. With a differential input voltage u2 = -u1, the output current is accordingly given by:

ia = 2gmu1/(1 + gmRE) = gmeu1


Notice that the transistor Q1 looks into a high impedance, such that all the current ia is carried on to the emitter follower, even if the signal output is single ended.


The transistor Q3 is configured as an emitter follower and in this configuration has the task to increase the current gain. The output current accordingly is 3ia (>>1).

The transistor Q4 is often referred to as the voltage amplifying stage. Notice that the input signal consists of a current (it is accordingly current driven). Since the quiescent collector current is set by a current generator, the output current ib is equal to 43ia. Because of the resistor RB, 4 is reduced compared to the current gain without this resistor. If the impedance at the collector of Q4 is denoted Zb, the output voltage accordingly is given by:

ub = 43iaZb


When Ia is inserted, this may be written:

ub = 43Zbgmeu1


If gm4 is denoting the transconductance of Q4, the effective current gain 4 for this transistor may be found as:

1/4 = 1/Q4 + 1/gm4RB


Notice that 4 is equal to the current gain Q4 at the quiescent point when RB is removed.

In figure 3.1 the capacitor CD determines the dominant pole. It should be chosen in such way that a suitable phase margin is achieved when feedback is employed. Negative feedback for the amplifier is here achieved by means of the two feedback resistors RF1 and RF2.


The transistors Q5 and Q6 are (separately) configured as emitter followers with the quiescent point determined by current generators. The following transistors Q7 and Q8 are in a similar way configured as emitter followers, now also with emitter resistors to prevent thermal runaway. Since the coupling is completely symmetric, it is relatively linear. In addition the loss between input and output is small since there is two double base emitter junctions in opposite directions.

The voltage gain is nearly one, while the current gain is very high, about 57. This is more than usual, where only one emitter follower is used. Here a form of biasing must be added. In practice it is however great variation in the voltage follower realisation. Since this is without any great importance to the figures, we will do with this single example of a voltage follower.

The fact that the voltage follower is designed completely symmetric, is improving the properties at DC and is reducing the even harmonic distortion.

Therefore it should be mentioned that some discrete operational amplifiers are fully symmetric designed from the same reasons.


The open loop gain for the complete amplifier in figure 3.1 is approximately given by eq. 3.4:

Ao = 43Zbgme


This may be found from eq. 3.3 supposing the voltage follower has a voltage gain of unity. This expression is valid before the effect of the compensation capacitor CD is taken into account. This will limit the open loop gain at higher frequencies to:

Ah = gme/(2πfCD)


The frequency corresponding to the dominant pole is given by:

fD = 1/(2πfCDZb)


Since open loop gain is frequency dependent, the closed loop gain also is. If the open loop gain is denoted A(s), the closed loop gain may be written as:

G(s) = uo(s)/ u1(s) = Go/[1 + Go/A(s)]


Here Go = 1 + RF2/RF1 is equal to the voltage gain with feedback when A(s) approaches infinity. To see the effect the gain setting Go has on the frequency response at closed loop, A(s) may be separated in A(s) = N(s)/D(s), where the numerator N(s) is containing the zeroes in the transfer function, while the denominator D(s) is containing the poles (included the dominant one determined by the capacitor CD). Equation 3.8 then becomes:

G(s) = uo(s)/ u1(s) = GoN(s)/[N(s) + GoD(s)]


It is seen that Go not only determines the value of the gain module as expected, but also is multiplying the effect of D(s) to the closed loop response.

In figure 3.2 is shown a typical transfer function when the capacitor CD determines the dominant pole in a such way that the response is falling with 20 dB/decade above the dominant frequency.


Figure 3.2. Typical transfer function of operational amplifier with dominant pole and voltage feedback.

Moreover, it is seen that at different closed loop gains the bandwidths will be different. But the gain bandwidth product is nearly constant, e.g. the bandwidth is halved when the gain is doubled. In other words is AofD nearly equal to G1f1 G2f2.


The designation 'Current Feedback' arises from the fact that current feedback is used instead of voltage feedback, which is used for conventional operational amplifiers. Current feedback operational amplifiers, like the conventional, are available as integrated circuits.

The amplifier has originated to deal with the problem of bandwidth and gain dependence of the conventional operational amplifier, discussed in the preceding chapter. The high number of gain stages and the configuration itself also result in high propagation delays and slew rate limitations.

In figure 4.1 is shown the principle for current feedback amplifiers.


Figure 4.1. Principle for current feedback amplifier.

A buffer at the input with a voltage gain of one forces the voltage u2 to follow the input voltage u1. The current i- running in or out of the terminal is amplified by a transimpedance amplifier to the output voltage uo.

The complex transfer function A(s) has ohm as denomination, and uo = i-A(s). The operation may be described by:

i- = i1 - i2 = u2/R1 - (uo - u2)/R2


Since uo = i-A(s) and u2 = u1 (because of the buffer), this gives:

uo/A(s) = u1(1/R1 + 1/R2)- uo/R2


Reorganizing eq. 4.1 with Go = 1 + R2/R1:

G(s) = uo/u1 = Go /[1 + R2/A(s)]


To once again see the effect the gain Go has on the frequency response in closed loop, A(s) may be separated in A(s) = N(s)/D(s), where the numerator N(s) contains the zeroes in the transfer function, while the denominator D(s) contains the poles. Equation 4.2 then becomes:

G(s) = uo/u1 = GoN(s)/[N(s) + R2D(s)]


If we compare this closed loop response with the response for conventional voltage feedback amplifiers in equation 3.9, it is seen that R2 has replaced Go in the frequency dependent clause in the denominator. Since R2 is constant, independent of the value of the closed loop gain (while this is not possible for Go), it is seen that the pole placement, and thereby the bandwidth, may be kept constant.

Changing the size of R1 is changing the gain, while changing the size of R2 is changing the bandwidth (if wanted). The most suppliers of integrated current feedback amplifiers design their amplifiers to operate with fixed values of R2. Thus these values are optimised relative to the circuits internal capacitances and for different load conditions. In some cases R2 is built in to optimise this variable and to minimise parasitic capacitances, especially in parallel to this resistor, which otherwise would have degraded the stability.

This type of amplifiers is not optimised for accuracy at high gains, neither for DC or AC. Their advantages are due to their very large bandwidth (several hundred MHz is quite common) and speed (several hundred V/s is typical).

A more detailed block schematic for explanation of how these amplifiers are working is shown in figure 4.2. The resistor RT represents the transresistance often stated in data sheets. The value of this normally is quite high (several tens of kiloohms is not unusual). The capacitor CT represents internal and added capacitor to provide for sufficient stability.


Figure 4.2. Block diagram for current feedback amplifier.

The value of this capacitor normally is very low (a few picofarads), as this is sufficient since the value of RT is very high. Notice that the current i- is providing for the charging and discharging of this capacitor. This, together with the absence of current limiting current generators, is the explanation of the high slew rate values that is achieved. The resistor R- in the figure represents the output resistance of the buffer. The current through this is mirrored through the transimpedance network (RT, CT) and makes the voltage at the input of the buffer A2. This is a voltage follower, thus the input and output voltage is nearly equal.

In figure 4.3 the closed loop gain as function of the frequency is shown for two different gain settings. It is seen that the bandwidth is nearly independent of the closed loop gain. As mentioned, this is in sharp contrast to the conventional voltage feedback operational amplifier.


Figure 4.3 Asymptotic course of gain with current feedback amplifier.

In figure 4.4 is shown an example of circuit diagram of a current feedback operational amplifier.


Figure 4.4. Circuit diagram of a current feedback amplifier.

The circuit is completely symmetric built up. This improves the properties at DC and reduces even harmonic distortion.

The transistors Q1-Q4 make the input buffer A1. This has a voltage gain of approximately one. The bases of Q1 and Q2 make the high impedance non-inverting input. The emitters of Q3 and Q4 thus make the low impedance inverting input. Since the circuit is symmetrical, the error current i- is fed to the two current mirrors (Q9/Q10 and Q11/Q12) and then to the summing point on the bases of Q5 and Q6.

The transresistance RT is high impedance, since this is the input impedance to the output buffer A2 consisting of Q5-Q8. Also this buffer has a voltage gain of nearly unity. The transcapacitance CT is made out of internal capacitances at the input of Q5 and Q6 plus the capacitors CD1 and CD2. These will determine the necessary phase margin to ensure the stability of the amplifier at the given gain and load RL connected to the output.

The resistor RF1 normally sets the gain, while RF2 is chosen to a value optimising bandwidth and/or slew rate.

Finally it should be mentioned that current feedback amplifiers often is used in inverting mode. This is achieved as for inverting conventional operational amplifiers (here the bases of Q1 and Q2 are grounded, while the lower end of RF1 is connected to the input signal instead of ground). It is then seen that Q3 and Q4 are coupled in common base. Accordingly the bandwidth is very large, and higher than for the non-inverting configuration. The drawback of course is that the input impedance is very low (approximately equal to RF1).



Knut Harald Nygaard